1. Field of the Invention
This invention relates to first-in-first-out buffers.
2. Description of Related Art
First-in first-out (FIFO) buffers are well known for intermediating data flow between devices. FIFO buffers have input and output ports which operate independently to allow devices connected to the FIFO buffer to write and read asynchronously. For example, a first device writes to the FIFO buffer via an input port, and a second device reads from the FIFO buffer via an output port to create a one-way data flow from the first device to the second device. FIFO buffers maintain read and write pointers which indicated where data is written or read so that the first values written into the FIFO buffer are the first values read out. Control logic handles handshake and/or flags signals to and from attached devices to control access and prevent the devices from trying to write to a full buffer or read from an empty buffer.
FIFO buffers have been implemented as integrated circuits (ICs) containing memory, input/output (I/O) ports, and control logic. FIFO buffer ICs flexible enough for a wide variety of applications are sought. One limit on FIFO buffer flexibility is memory size which may be insufficient for some applications. A large memory increases the number of applications of the FIFO buffer IC but also increases manufacturing costs. Another limit on a FIFO buffer's flexibility is its input/output (I/O) interface. For example, an IC containing the two FIFO buffers can provide a bi-directional data path, but some devices which would attach to a FIFO buffer require a bi-directional port while other devices require separate input and output ports. Additionally, data widths (i.e. the number of parallel bits contained in a data signal) vary from device to device. A FIFO buffer which has only bi-directional ports or only separate input and output ports or ports with fixed data widths is limited in its applications.